1. Field of the Invention
The present invention generally relates to programmable logic devices. More specifically, the present invention relates to input/output (I/O) capabilities of programmable logic devices.
2. Description of the Related Art
A programmable logic device (PLD) is a programmable integrated circuit that allows the user of the circuit, using software control, to program particular logic functions the circuit will perform. Logic functions performed by small, medium, and large-scale integration integrated circuits can instead be performed by programmable logic devices. When an integrated circuit manufacturer supplies a typical programmable logic device, it is not yet capable of performing any specific function. The user, in conjunction with software supplied by the manufacturer or created by the user or an affiliated source, can program the PLD to perform particular function or functions required by the user's application. The PLD then can function in a larger system designed by the user just as though dedicated logic chips were employed. For the purpose of this description, it is to be understood that a programmable logic device refers to once programmable devices as well as reprogrammable devices.
Programmable logic encompasses all digital logic circuits that are configured by the end user, including PLDs, field programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs). Referring initially to FIGS. 1 and 2, a CPLD with an embedded array programmable logic design will be described. Although only a few logic array blocks or memory blocks are illustrated, it should be appreciated that any number may be provided in order to meet the needs of a particular system.
The general architecture of the embedded array programmable logic design will be generally familiar to those knowledgeable of the FLEX10K.TM. logic family of devices manufactured by the Altera Corporation of San Jose, Calif. Such an architecture, for example, is also described in U.S. Pat. No. 5,550,782 and Altera Data Book 1996, both of which are incorporated herein by reference.
Referring initially to FIG. 1, a CPLD 100 includes a core region 120 coupled to a plurality of bi-directional ports 160 included within a peripheral region 121. Peripheral region 121 also includes a peripheral bus 150 coupled to each of the plurality of ports 160 by way of an associated peripheral bus interface 170. A bi-directional data bus 172 couples each port 160 to a plurality of conductors 190 by way of an associated data multiplexer 110. The data bus 172 is arranged to pass data between each associated one of the plurality of ports 160 and selected row or column channels respectively included (but not shown) in each of the plurality of conductors 190. Unfortunately, the peripheral bus 150 is designed to only carry a variety of control and clock signals (e.g. output enable (OE), data latch clear (CL), and system clock (CLK)) between each of the plurality of ports 160 and is therefore not capable of carrying any data signals. As a consequence, data may only pass between the ports 160 and the plurality of conductors 190 by way of its associated data bus 172.
By way of example, bi-directional port 160 is coupled to peripheral bus 150 by way of peripheral bus interface 170 that includes a plurality of control and clock signals connectors. Bi-directional port 160 is also selectively coupled to a horizontal conductor 190 (and all row channels included therein) by way of a data multiplexer 110 so that core region 120 may communicate with external circuitry connected to bi-directional port 160. Such external circuitry may, for example, include systems such as Pentium.TM. based PCs or Sun SPARCstations.TM.. Such systems being capable of executing automatic place and route software such as, for example, MAX+PLUS II.TM. developed by the Altera Corporation of San Jose, Calif. In a procedure known in the art as fitting a logic function, such automatic place and route software is used to logically couple previously programmed logic and memory units included within core region 120. In this manner, CPLD 100 is programmed to perform the logic function as desired.
Fitting a logic function requires the place and route software to first logically couple a selected set of previously programmed logic array blocks (LABs) and embedded array blocks (EABs) located in core region 120. Each EAB includes an array of memory cells. Each LAB includes a plurality of logic elements (LE) each of which are capable of performing simple logic functions. A logic interconnect included within each LAB serves to interconnect each of the logic elements included therein. As shown in FIG. 1, core region 120 includes a plurality of LABs 102 and a plurality of EABs 104 programmably interconnected by way of plurality conductors 180 to form a logic and memory array. By way of example, LABs 102a, 102b and EAB 104a are coupled by way of conductor 190 such that port 160 may selectively access LAB 102a, LAB 102b or EAB 104a by way of data multiplexer 110.
In some instances, fitting a logic function may require a bi-directional port to access logic or memory blocks coupled with conductors associated with other bi-directional ports. Unfortunately, since conventionally each bi-directional port can only access its associated conductor, it is often necessary to cross couple selected ones of the conductors (including the associated plurality of row channels and column channels therein). In order to accomplish this cross coupling of conductors, a programmable routing mux (PRM) 136 is used. The PRM 136 that includes a plurality of programmable connectors each capable of selectively coupling a selected row channel and a selected column channel included in each of the cross coupled conductors. In this manner, a port may access logic array blocks (and logic elements therein) and/or memory blocks associated with another port. Unfortunately, the programmable connectors used are often limited in number and may prove insufficient to meet the needs of particular logic fitting routine.
The interconnections of PRM 136, logic array block 102a and its associated plurality of logic elements 106a-106h, horizontal conductor 190 and its associated plurality of row channels 190a, and vertical conductor 192 and its associated plurality of column channels 192a are illustrated in FIG. 2. PRM 136 includes an array of programmable connectors 138 capable of selectably coupling any of the plurality of row channels 190a and any of the plurality of column channels 192a. A programmable connector 138a is represented as a single programmable bit, however, it should be noted that any suitable programmable connector type device may be used.
In order to fit the desired logic function, various logic elements may be individually configured to perform a small but crucial part of the overall logic function. Any automatic routing and placing software must then logically connect all the programmed logic elements (and in some cases, memory included in the various EABs) such that CPLD 100 may execute the desired logic function. By way of example, in order for logic element 106a to be accessed by row channel 190a such that port 160 may access logic element 106a, multiplexer 108 may selectively enable data line 109. Enable data line 109 is then programmably coupled to row channel 190a by way of programmable connectors 132a within programmable connection 132 such that port 160 may access logical element 106a. Programmable connector 132a would then not be available for other connections until released. Unfortunately, even if port 160 is able to connect to desired logic elements in logic array block 102a, the path may be so circuitous as to create a slow data path which may prove to be unacceptable for the application at hand.
Alternatively, if it is required that a port 162 couple to logic element 106a of the LAB 102a, programmable resources in addition to those discussed above would be required since it would be necessary to couple conductor 194, for example, to conductor 192 and then to conductor 190 to be able to utilize enable data line 109. As can be seen, the need to form circuitous links within core region 120 may use substantial numbers of programmable connectors 138a which may be of limited availability.
A very complex logic function may require more connections than the number of available programmable connectors is able to provide. In this case, the fitting is said to have failed. This problem is exacerbated by the fact that each bi-directional port in CPLD 100 may access only its associated conductor such that additional programmable connectors are consumed in order to access LABs or EABs associated with other conductors.
In view of the foregoing, it is advantageous and therefore desirable to have available a programmable logic device which is capable of coupling together adjacent bi-directional ports such that each may access each others associated conductor without using substantially any core region programmable connectors. In this manner, ports may access logic elements and memory blocks without using substantially any core region programmable connectors. By reducing the number of core region programmable connectors consumed in fitting a particular logic function, the complex programmable logic device will have a higher success rate in fitting logic functions.